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參數(shù)資料
| 型號： | MT90823AP |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 3V Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQCC84 |
| 封裝： | PLASTIC, MS-018AF, LCC-84 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 663K |
| 代理商： | MT90823AP |
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MT90823
Data Sheet
17
Zarlink Semiconductor Inc.
Table 8 - Interface Mode Selection (IMS) Register Bits
Table 9 - Serial Data Rate Selection (16 input x 16 output)
Bit
Name
Description
15-10
Unused
Must be zero for normal operation.
9-5
BPD4-0
Block Programming Data.
These bits carry the value to be loaded into the
connection memory block whenever the memory block programming feature is
activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to
1, the contents of the bits BPD4- 0 are loaded into bit 15 to bit 11 of the connection
memory. Bit 10 to bit 0 of the connection memory are set to 0.
4
BPE
Begin Block programming Enable.
A zero to one transition of this bit enables the
memory block programming function. The BPE and BPD4-0 bits in the IMS register
have to be defined in the same write operation. Once the BPE bit is set high, the
device requires two frames to complete the block programming. After the
programming function has finished, the BPE bit returns to zero to indicate the
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort
the programming operation.
When BPE = 1, the other bits in the IMS register must not be changed for two frames
to ensure proper operation.
3
OSB
Output standby.
When ODE = 0 and OSB = 0, the output drivers of STo0 to STo15
are in high impedance mode. When ODE = 0 and OSB = 1, the output driver of STo0
to STo15 function normally. When ODE = 1, STo0 to STo15 output drivers function
normally.
2
SFE
Start Frame Evaluation.
A zero to one transition in this bit starts the frame evaluation
procedure. When the CFE bit in the FAR register changes from zero to one, the
evaluation procedure stops. To start another frame evaluation cycle, set this bit to
zero for at least one frame.
1 - 0
DR1-0
Data Rate Select.
Input/Output data rate selection. See Table 9 for detailed
programming.
DR1
DR0
Data Rate Selected
Master Clock Required
0
0
2.048 Mb/s
4.096 MHz
0
1
4.096 Mb/s
8.192 MHz
1
0
8.192 Mb/s
16.384 MHz
1
1
Reserved
Reserved
Read/Write Address:
Reset Value:
01
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
DR0
DR1
BPD
1
BPD
2
BPD
3
0
14
15
BPD
0
0
BPD
4
BPE
OSB
SFE
0
0
0
0
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PDF描述 |
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| MT90826 | Quad Digital Switch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90823AP1 | 制造商:Microsemi Corporation 功能描述:LOW VOL LARGE DIGITAL SWCH |
| MT90826 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad Digital Switch |
| MT90826AG | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160MQFP - Trays |
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