- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄229296 > MT48V8M16LFF4-10XT 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號： | MT48V8M16LFF4-10XT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 5/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48V8M16LFF4-10XT |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
13
2001 Micron Technology, Inc. All rights reserved.
length is set to two; by A2-A8 (x16) or A2-A7 (x32) when
the burst length is set to four; and by A3-A8 (x16) or A3-
A7 (x32) when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3. Note only a
sequential burst is allowed for full page bursts.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6 on page 14.
Figure 7: Mode Register Definition
10
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7 A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
Reserved WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
BA0
BA1
M9
M7 M6 M5 M4
M3
M8
M2 M1 M0
M10
11
A11
M11
M12
M13
MR
13
12
Mode Register Definition
Program Mode Register
Program Extended Mode Register
0
1
0
M13
M12
Valid
-
M9
0
-
M10
0
-
M11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L256V36PT-6 | 256K X 36 ZBT SRAM, 3.5 ns, PQFP100 |
| MT5C2561EC-45IT | 256K X 1 STANDARD SRAM, 45 ns, CQCC28 |
| M378T3253FG0-CE6 | 32M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| M93C06-DS3TG | 16 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| M93C06-WDS7 | 16 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48V8M16LFF4-8 XT | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。