- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄229296 > MT48V8M16LFF4-10XT 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號： | MT48V8M16LFF4-10XT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 26/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48V8M16LFF4-10XT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
32
2001 Micron Technology, Inc. All rights reserved.
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sam-
pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in
Figure 29 and Figure 30.)
Figure 29: Clock Suspend During WRITE
Burst
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
Figure 30: Clock Suspend During READ
Burst
DON’T CARE
DIN
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
n
NOP
CLK
T2
T1
T4
T3
T5
T0
CKE
INTERNAL
CLOCK
NOP
DIN
n + 1
DIN
n + 2
NOTE: For this example, burst length = 4 or greater, and DM
is LOW.
TRANSITIONING DATA
DON’T CA
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
MAND
DDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, a
DQM is LOW.
CKE
TERNAL
CLOCK
NOP
TRANSITIONING DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L256V36PT-6 | 256K X 36 ZBT SRAM, 3.5 ns, PQFP100 |
| MT5C2561EC-45IT | 256K X 1 STANDARD SRAM, 45 ns, CQCC28 |
| M378T3253FG0-CE6 | 32M X 64 DDR DRAM MODULE, 0.45 ns, DMA240 |
| M93C06-DS3TG | 16 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| M93C06-WDS7 | 16 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48V8M16LFF4-8 XT | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。