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| 型號： | MT48V8M16LFF4-10XT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 19/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48V8M16LFF4-10XT |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
26
2001 Micron Technology, Inc. All rights reserved.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 19 for each possible CAS latency; data element
n + 3 is the last desired data element of a longer burst.
Figure 19: Terminating a READ Burst
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE
NOP
T7
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE
NOP
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
BURST
TERMINATE
NOP
X = 0 cycles
CAS Latency = 1
X = 1 cycle
CAS Latency = 2
CAS Latency = 3
X = 2 cycles
TRANSITIONING DATA
NOTES:
1) Page remains open after a Burst Terminate command
2) N+3 is either the last data element of a burst of four, or the last desired dta element of a longer burst.
3) DQM is LOW.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48V8M16LFF4-8 XT | 制造商:Micron Technology Inc 功能描述: |
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