參數(shù)資料
型號(hào)： MT48V8M16LFF4-10XT
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁數(shù)： 43/69頁
文件大?。?/td> 6213K
代理商： MT48V8M16LFF4-10XT
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
48
2001 Micron Technology, Inc. All rights reserved.
Figure 35: Initialize and Load Mode Register
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE
command, RA = Row Address, BA = Bank Address
3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur
prior to an Active command
4. Optional refresh command.
5. Although not required, to prevent bus contention it is suggested to keep DQM high during the Initialization sequence.
CKE
BA0, BA1
Load Extended
Mode Register
Load Mode
Register
tCKS
Power-up:
VDD and
CLK stable
T = 100s
tCKH
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DQML, DQMU5
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DQ
High-Z
A0-A9, A11
RA
A10
RA
ALL BANKS
CLK
tCK
LMR3
NOP
PRE
LMR3
AR
AR4
ACT
tCMS tCMH
BA0 = L,
BA1 = H
tAS tAH
tAS tAH
BA0 = L,
BA1 = L
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CODE
tAS tAH
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PRE
ALL BANKS
tAS tAH
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T0
T1
T3
T5
T7
T9
T19
T29
DON’T CARE
BA
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tRP
tMRD
tRP
tRFC
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COMMAND1,2
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