參數(shù)資料
型號(hào)： MT48V8M16LFF4-10XT
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁(yè)數(shù)： 38/69頁(yè)
文件大小： 6213K
代理商： MT48V8M16LFF4-10XT
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
43
2001 Micron Technology, Inc. All rights reserved.
Table 14:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 47
AC CHARACTERISTICS
PARAMETER
SYMBOL
-75M
-8
-10
UNITS NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Access time from CLK (positive. edge)
CL = 3
tAC (3)
5.4
7
ns
CL = 2
tAC (2)
6
8
ns
CL = 1
tAC (1)
na
19
22
ns
Address hold time
tAH
0.8
11ns
Address setup time
tAS
1.5
2.5
ns
CLK high-level width
tCH
3
33ns
CLK low-level width
tCL
2.5
33ns
Clock cycle time
CL = 3
tCK (3)
7.5
8
10
ns
CL = 2
tCK (2)
9.6
12
ns
CL = 1
tCK (1)
n/a
20
25
ns
CKE hold time
tCKH
1
11ns
CKE setup time
tCKS
2.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
0.8
11ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
2.5
ns
Data-in hold time
tDH
0.8
11ns
Data-in setup time
tDS
1.5
2.5
ns
Data-out high-impedance time
CL = 3
tHZ (3)
5.4
7
ns
CL = 2
tHZ (2)
6
8
ns
CL = 1
tHZ (1)
na
19
22
ns
Data-out low-impedance time
tLZ
1
11ns
Data-out hold time (load)
tOH
2.5
ns
Data-out hold time (no load)
tOHN
1.8
ns
ACTIVE to PRECHARGE command
tRAS
44
120,000
48
120,000
50
120,000
ns
ACTIVE to ACTIVE command period
tRC
66
80
100
ns
ACTIVE to READ or WRITE delay
tRCD
19
20
ns
Refresh period (4,096 rows)
tREF
64
ms
AUTO REFRESH command period
tRFC
66
80
100
ns
PRECHARGE command period
tRP
19
20
ns
ACTIVE bank a to ACTIVE bank b
command
tRRD
2
tCK
Transition time
tT
0.3
1.2
0.5
1.2
0.5
1.2
ns
WRITE recovery time
Auto Precharge Mode
Manual Precharge Mode
tWR (a)
1 CLK
+7.5ns
1 CLK
+7ns
1 CLK
+5ns
tWR (m)
15
ns
Exit SELF REFRESH to ACTIVE command
tXSR
67
80
100
ns
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參數(shù)描述
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