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| 型號： | MT46V32M8FG-6TIT:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| 封裝： | (8 X 14) MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 88/93頁 |
| 文件大?。?/td> | 3632K |
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PDF: 09005aef80768abb/Source: 09005aef82a95a3a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
87
2003 Micron Technology, Inc. All rights reserved.
256Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 52:
Bank WRITE – with Auto Precharge
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
order.
5. See Figure 50 on page 85 for detailed DQ timing.
AUTO REFRESH
During auto refresh, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of tREFI (MAX).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 × tREFI(= tREFC). JEDEC specifications only support 8 × tREFI; Micron
specifications exceed the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates, internal to the DDR SDRAM, to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between
updates.
Command
NOP
1
NOP
1
NOP
1
NOP
1
NOP
1
NOP
1
NOP
1
WRITE
2
3
DQ
4
Address
Row
CK
CK#
CKE
A10
BA0, BA1
tCK
tCH
tCL
tIS
tIH
tIS
tIH
tIS
tIH
tRCD
tRAS
tRP
tWR
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T4n
ACT
Col n
Bank x
tDQSL
tDQSH tWPST
DQS
DM
DI
b
tDS
tDH
tDQSS (NOM)
Don’t Care
Transitioning Data
tWPRES tWPRE
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