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參數(shù)資料
| 型號： | MT46HC32M16LGCM-54IT:B |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 5.4 ns, PBGA90 |
| 封裝： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁數(shù)： | 47/98頁 |
| 文件大?。?/td> | 3258K |
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Standard Mode Register
The standard mode register bit definition enables the selection of burst length, burst
type, CAS latency (CL), and operating mode, as shown in Figure 18. Reserved states
should not be used as this may result in setting the device into an unknown state or
cause incompatibility with future versions of LPDDR devices. The standard mode regis-
ter is programmed via the LOAD MODE REGISTER command (with BA0 = 0 and BA1 =
0) and will retain the stored information until it is programmed again, until the device
goes into deep power-down mode, or until the device loses power.
Reprogramming the mode register will not alter the contents of the memory, provided
it is performed correctly. The mode register must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait tMRD before initiating the subse-
quent operation. Violating any of these requirements will result in unspecified operation.
Figure 18: Standard Mode Register Definition
M3 = 0
Reserved
2
4
8
16
Reserved
M3 = 1
Reserved
2
4
8
16
Reserved
M3
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
0
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Standard mode register (Mx)
Address bus
9
7 6
5
4
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
Operating Mode
A10
An ...
BA0
BA1
10
...
n
0
n+ 1
n+ 2
Mn
0
–
M10
0
–
M9
0
–
M8
0
–
Operating Mode
Normal operation
All other states reserved
0
1
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
Mn + 2
0
1
0
1
Mn + 1
M7
0
–
...
Note: 1. The integer n is equal to the most significant address bit.
Burst Length
Read and write accesses to the device are burst-oriented, and the burst length (BL) is
programmable. The burst length determines the maximum number of column loca-
512Mb: x16, x32 Mobile LPDDR SDRAM
Standard Mode Register
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
51
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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| MT46V128M4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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