- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299522 > MT46HC32M16LGCM-54IT:B 32M X 16 DDR DRAM, 5.4 ns, PBGA90 PDF資料下載
參數(shù)資料
| 型號： | MT46HC32M16LGCM-54IT:B |
| 元件分類： | DRAM |
| 英文描述： | 32M X 16 DDR DRAM, 5.4 ns, PBGA90 |
| 封裝： | 10 X 13 MM, GREEN, PLASTIC, VFBGA-90 |
| 文件頁數(shù)： | 21/98頁 |
| 文件大?。?/td> | 3258K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
Table 11: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all parameters in this table; VDD/VDDQ = 1.70–1.95V
Parameter
Symbol
-5
-54
-6
-75
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active bank a to active bank b
command
tRRD
10
–
10.8
–
12
–
15
–
ns
Read of SRR to next valid
command
tSRC
CL + 1
–
CL + 1
–
CL + 1
–
CL + 1
–
tCK
SRR to read
tSRR
2
–
2
–
2
–
2
–
tCK
DQS write preamble
tWPRE
0.25
–
0.25
–
0.25
–
0.25
–
tCK
DQS write preamble setup time
tWPRES
0
–
0
–
0
–
0
–
ns
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write recovery time
tWR
15
–
15
–
15
–
15
–
ns
Internal WRITE-to-READ
command delay
tWTR
2
–
2
–
2
–
1
–
tCK
Exit power-down mode to first
valid command
tXP
2
–
2
–
1
–
1
–
tCK
Exit self refresh to first valid
command
tXSR
120
–
120
–
120
–
120
–
ns
Notes: 1. All voltages referenced to VSS.
2. All parameters assume proper device initialization.
3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nomi-
nal supply voltage levels, but the related specifications and device operation are guaran-
teed for the full voltage ranges specified.
4. The circuit shown below represents the timing reference load used in defining the rele-
vant timing parameters of the device. It is not intended to be either a precise representa-
tion of the typical system environment or a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate
the timing reference load to system environment. Specifications are correlated to produc-
tion test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH
are expected to be in the same range. However, these parameters are not subject to
production test but are estimated by design/characterization. Use of IBIS or other simula-
tion tools for system design validation is suggested.
I/O
20pF
I/O
10pF
Full drive strength
Half drive strength
50
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference voltage level for signals other than CK/
CK# is VDDQ/2.
6. A CK and CK# input slew rate
≥1 V/ns (2 V/ns if measured differentially) is assumed for
all parameters.
7. All AC timings assume an input slew rate of 1 V/ns.
512Mb: x16, x32 Mobile LPDDR SDRAM
Electrical Specifications – AC Operating Conditions
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
28
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H32M16BT-37VL:A | 32M X 16 DDR DRAM, 0.5 ns, PBGA92 |
| MT47H64M16HQ-3IT:G | 64M X 16 DDR DRAM, 0.4 ns, PBGA60 |
| MT47H64M8CF-5EAT:F | DDR DRAM, PBGA60 |
| MT48H16M16LFBF-10IT | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| MT48LC8M16A2BB-6ALIT:G | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V128M4 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。