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參數(shù)資料
| 型號： | MT28F640J3BS-12MET |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64 |
| 封裝： | 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 8/54頁 |
| 文件大小： | 587K |
| 代理商： | MT28F640J3BS-12MET |
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128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
09005aef80b5a323
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F640J3_J.fm – Rev. J 2/26/04 EN
16
2004 Micron Technology. Inc.
NOTE:
1. Commands other than those shown in Table 4 on page 15 are reserved for future device implementations and
should not be used.
2. The SCS is also referred to as the extended command set.
3. Bus operations are defined in Table 3 on page 14.
4. X
= Any valid address within the device
BA = Address within the block
IA
= Identifier code address; see Figure 9 on page 13 and Table 16 on page 24
QA = Query data base address
PA = Address of memory location to be programmed
5. ID
= Data read from identifier codes
QD = Data read from query data base
SRD = Data read from status register; see Table 17 on page 25 for a description of the status register bits
PD = Data to be programmed at location PA; data is latched on the rising edge of WE#
CC = Configuration code
6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.
7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock
codes. See Block Status Register section for read identifier code data.
8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 are placed in High-Z.
9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.
10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count
ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third
and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command
(D0h) is expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the
WRITE-to-BUFFER operation. Please see Figure 11 on page 32, WRITE-to-BUFFER Flowchart, for additional informa-
tion.
11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.
12. Attempts to issue a block erase or program to a locked block will fail.
13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.
14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.
The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT28F640J3FS-11 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F640J3FS-115 ET | 制造商:Micron Technology Inc 功能描述:NAND Flash Parallel 3.3V 64Mbit 8M/4M x 8bit/16bit 115ns 64-Pin FBGA Tray 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 115NS 64FBGA |
| MT28F640J3FS-115 ET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| MT28F640J3FS-115 GMET | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT28F640J3FS-115 GMET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應商設備封裝:48-CBGA（7x7） 包裝:托盤 |
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