- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299522 > MT28F640J3BS-12MET 4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64 PDF資料下載
參數(shù)資料
| 型號： | MT28F640J3BS-12MET |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, 120 ns, PBGA64 |
| 封裝： | 10 X 13 MM, 1 MM PITCH, LEAD FREE, FBGA-64 |
| 文件頁數(shù)： | 5/54頁 |
| 文件大?。?/td> | 587K |
| 代理商： | MT28F640J3BS-12MET |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
09005aef80b5a323
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F640J3_J.fm – Rev. J 2/26/04 EN
13
2004 Micron Technology. Inc.
wake-up interval, normal operation is restored. The
command execution logic (CEL) is reset to the read
array mode and the status register is set to 80h.
During block erase, program, or lock bit configura-
tion, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maxi-
mum time of tPLPH + tPHRH, until the RESET opera-
tion is complete. Any memory content changes are no
longer valid; the data may be partially corrupted after a
program or partially changed after an erase or lock bit
configuration. After RP# goes to logic HIGH (VIH), and
after tRS, another command can be written.
It is important to assert RP# during system reset.
After coming out of reset, the system expects to read
from the Flash memory. During block erase, program,
or lock bit configuration mode, automated Flash
memories provide status information when accessed.
When a CPU reset occurs with no Flash memory reset,
proper initialization may not occur because the Flash
memory may be providing status information instead
of array data. Micron Flash memories allow proper ini-
tialization following a system reset through the use of
the RP# input. RP# should be controlled by the same
RESET# signal that resets the system CPU.
Read Query
The READ QUERY operation produces block status
information, CFI ID string, system interface informa-
tion, device geometry information, and extended
query information. READ QUERY information is only
accessed by executing a single-word READ.
Read Identifier Codes
The READ IDENTIFIER CODES operation produces
the manufacturer code, device code, and the block
lock configuration codes for each block (see Figure 9).
The block lock configuration codes identify locked and
unlocked blocks.
Write
Writing commands to the CEL allows reading of
device data, query, identifier codes, and reading and
clearing of the status register. In addition, when VPEN =
VPENH, block erasure, program, and lock bit configura-
tion can also be performed.
The BLOCK ERASE command requires suitable
command data and an address within the block. The
BYTE/WORD PROGRAM command requires the com-
mand and address of the location to be written to. The
CLEAR BLOCK LOCK BITS command requires the
command and any address within the device. Set
BLOCK LOCK BITS command requires the command
and the block to be locked. The CEL does not occupy
an addressable memory location. It is written to when
the device is enabled and WE# is LOW. The address
and data needed to execute a command are latched on
the rising edge of WE# or the first edge of CEx that dis-
ables the device (see Table 2 on page 12). Standard
microprocessor write timings are used.
Figure 9: Device Identifier Code
Memory Map
NOTE:
When obtaining these identifier codes, A0 is not used in
either x8 or x16 modes. Data is always given on the
LOW byte in x16 mode (upper byte contains 00h).
Reserved for Future
Implementation
Manufacturer Code
Device Code
010000h
00FFFFh
000004h
000003h
000002h
000001h
000000h
Reserved for Future
Implementation
Reserved for Future
Implementation
Reserved for Future
Implementation
Block 63
Block 0
3FFFFFh
3F0003h
3F0002h
3F0000h
3EFFFFh
1EFFFFh
1F0003h
1F0002h
1F0000h
01FFFFh
010003h
010002h
32
Mb
64Mb
128Mb
Block 63 Lock Configuration
Block 0 Lock Configuration
Reserved for Future
Implementation
(Blocks 32 through 62)
Reserved for Future
Implementation
7FFFFFh
7F0003h
7F0002h
7F0000h
7EFFFFh
Block 127 Lock Configuration
Reserved for Future
Implementation
Block 31
Reserved for Future
Implementation
(Blocks 2 through 30)
Block 1
Reserved for Future
Implementation
Block 1 Lock Configuration
Block 127
Block 31 Lock Configuration
(Blocks 64 through 126)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT29F4G08FABWGXXXXET | 512M X 8 FLASH 2.7V PROM, PDSO48 |
| MT2LSYT3272T1G-11P | 32K X 72 CACHE SRAM MODULE, 11 ns, DMA160 |
| MT2LSYT3272T1G-12P | 32K X 72 CACHE SRAM MODULE, 12 ns, DMA160 |
| MT333X | GENERAL PURPOSE AUDIO CONNECTOR, JACK |
| MT36JBZS51272PIY-1G3XX | DDR DRAM MODULE, DMA240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT28F640J3FS-11 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Q-FLASHTM MEMORY |
| MT28F640J3FS-115 ET | 制造商:Micron Technology Inc 功能描述:NAND Flash Parallel 3.3V 64Mbit 8M/4M x 8bit/16bit 115ns 64-Pin FBGA Tray 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 115NS 64FBGA |
| MT28F640J3FS-115 ET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| MT28F640J3FS-115 GMET | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869 |
| MT28F640J3FS-115 GMET TR | 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。