參數(shù)資料
型號: MT18VDVF6472DG-262XX
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝: DIMM-184
文件頁數(shù): 9/38頁
文件大?。?/td> 713K
代理商: MT18VDVF6472DG-262XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
17
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Voltage on VDD supply, relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ supply, relative to VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and inputs, relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O pins, relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Operating temperature
TA (ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C
Storage temperature (plastic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Short circuit output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Table 9:
DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14; notes appear on pages 22–26; 0°C
≤ T
A ≤ +70°C
Parameter/Condition
Symbol
Min
Max
Units
Notes
Supply Voltage
VDD
2.3
2.7
V
I/O Supply Voltage
VDDQ
2.3
2.7
V
I/O Reference Voltage
VREF
0.49 X
VDDQ
0.51 X
VDDQ
I/O Termination Voltage (system)
VTT
VREF - 0.04 VREF + 0.04
V
7, 39
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.15
VDD + 0.3
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.3
VREF - 0.15
V
INPUT LEAKAGE CURRENT
Any input 0V
≤ VIN ≤ VDD, VREF pin 0V ≤ VIN
1.35V (All other pins not under test = 0V)
Command/
Address, RAS#,
CAS#, WE#, S#,
CKE
II
-5
5
A
CK, CK#
-10
10
DM
-4
4
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V
≤ VOUT ≤ VDDQ)
DQ, DQS
IOZ
-10
10
A
OUTPUT LEVELS
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
IOH
-16.8
mA
IOL
16.8
mA
Table 10:
AC Input Operating Conditions
Notes: 1–5, 14, 48; notes appear on pages 22–26; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
Parameter/Condition
Symbol
Min
Max
Units
Notes
Input High (Logic 1) Voltage
VIH(AC)VREF + 0.310
V
Input Low (Logic 0) Voltage
VIL(AC)–
VREF - 0.310
V
I/O Reference Voltage
VREF(AC)
0.49 X VDDQ0.51 X VDDQV
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