參數(shù)資料
型號： MT18VDVF6472DG-262XX
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁數(shù)： 13/38頁
文件大?。?/td> 713K
代理商： MT18VDVF6472DG-262XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
20
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Electrical Specifications
Table 13:
Capacitance (512MB only)
Note: 11; notes appear on pages 22–26
Parameter
Symbol
Min
Max
Units
Input/Output Capacitance: DQ, DQS, DM
CI0
810
pF
Input Capacitance: Command and Address, S#, CKE
CI1
2.5
3.5
pF
Input Capacitance: CK, CK#
CI2
–
4pF
Table 14:
Electrical Characteristics and Recommended AC Operating Conditions
DDR SDRAM components only
Notes: 1–5, 12–15, 29, 48; notes appear on pages 22–26; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
AC Characteristics
-335
-262
-26A/-265
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
Access window of DQs from CK/CK#
tAC
-0.7
+0.7
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock cycle time
CL = 2.5
tCK (2.5)
6
13
7.5
13
7.5
13
ns
CL = 2
tCK (2)
7.5
13
7.5/10
13
7.5/10
13
ns
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
0.35
0.5
ns
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
ns
Address and control input hold time (fast slew
rate)
tIH
F
0.75
0.90
.90
ns
Address and control input setup time (fast slew
rate)
tIS
F
0.75
0.90
.90
ns
Address and control input hold time (slow slew
rate)
tIH
S
0.80
1
ns
Address and control input setup time (slow slew
rate)
tIS
S
0.80
1
ns
Address and Control input pulse width (for each
input)
tIPW
2.20
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQH
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
ns
Data hold skew factor
tQHS
0.50
0.75
ns
ACTIVE to PRECHARGE command
tRAS
42
120,000
40
120,000
40
120,000
ns
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
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