參數(shù)資料
型號： MT18VDVF6472DG-262XX
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁數(shù)： 10/38頁
文件大?。?/td> 713K
代理商： MT18VDVF6472DG-262XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
18
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Electrical Specifications
Table 11:
IDD Specifications and Conditions – 512MB
DDR SDRAM Components Only
Notes: 1–5, 8, 10, 12, 47; notes appear on pages 22–26; 0°C
≤ T
A ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V
Max
Parameter/Condition
Sym
-335
-262
-26A/
-265
Units
Notes
OPERATING CURRENT: One device bank; Active-Precharge; tRC =
tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once
per clock cyle; Address and control inputs changing once every two
clock cycles
IDD0a
1,161
981
mA
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address
and control inputs changing once per clock cycle
IDD1a
1,566
1,476
1,341
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDD2Pb
72
mA
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK =
tCK MIN; CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM
IDD2Fb
900
810
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3Pb
540
450
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM andDQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
IDD3Nb
1,080
900
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4Ra
1,611
1,386
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing
twice per clock cycle
IDD4Wa
1,611
1,386
mA
AUTO REFRESH CURRENT
tREFC = tRFC (MIN)
IDD5b
4,590
4,230
mA
tREFC = 7.8125s
IDD5Ab
108
mA
SELF REFRESH CURRENT: CKE
≤ 0.2V
IDD6b
72
mA
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address
and control inputs change only during Active READ, or WRITE
commands
IDD7a
3,726
3,186
mA
Note:
a: Value calculated as one module rank in this operating condition, and all other module
ranks in IDD2p (CKE LOW) mode.
b: Value calculated reflects all module ranks in this operating condition.
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