參數(shù)資料
型號(hào)： MT18VDVF6472DG-262XX
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁數(shù)： 17/38頁
文件大小： 713K
代理商： MT18VDVF6472DG-262XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
24
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Notes
Figure 7:
Derating Data Valid Window (tQH - tDQSQ)
32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not
more than +400mV or 2.9V max, whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either -300mV or 2.2V min, whichever is
more positive. However, the DC average cannot be below 2.3V minimum.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current from minimum to maximum pro-
cess, temperature and voltage will lie within the outer bounding lines of the V-I
b. The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure 8, "Pull-Down," on page 25.
c. The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
d. The variation in driver pull-up current within nominal limits of voltage and tem-
perature is expected, but not guaranteed, to lie within the inner bounding lines
e. The full variation in the ratio of the maximum to minimum pull-up and pull-
down current should be between 0.71 and 1.4, for device drain-to-source volt-
ages from 0.1V to 1.0V, and at the same voltage and temperature.
f. The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.
34. The voltage levels used are derived from a minimum VDD level and the referenced test
load. In practice, the voltage levels obtained from a properly terminated bus will pro-
vide significantly different voltage values.
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
ns
-335
-262/-26A/-265 @ tCK = 10ns
-262/-26A/-265 @ tCK = 7.5ns
NA
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