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參數(shù)資料
| 型號(hào)： | MT18HTF12872DG-40EXX |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | DIMM-240 |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 717K |
| 代理商： | MT18HTF12872DG-40EXX |
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512MB, 1GB, 2GB (x72, DR, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
PRELIMINARY
09005aef80e934a6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72DG_A.fm - Rev. A 10/03 EN
14
2003 Micron Technology. Inc.
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to
make the command and data bus efficient for sustain-
able bandwidths in DDR2 SDRAM. Bits E3–E5 define
the value of AL as shown in Figure 7. Bits E3–E5 allow
the user to program the DDR2 SDRAM with a CAS#
Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states
should not be used as unknown operation or incom-
patibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ
or WRITE command to be issued prior to tRCD (MIN)
with the requirement that AL
tRCD(MIN). A typical
application using this feature would set AL = tRCD
(MIN) - 1 x tCK. The READ or WRITE command is held
for the time of the additive latency (AL) before it is
issued internally to the DDR2 SDRAM device. READ
Latency (RL) is controlled by the sum of the Posted
CAS additive latency (AL) and CAS Latency (CL); RL =
AL + CL. Write latency (WL) is equal to READ latency
minus one clock; WL = AL + CL - 1 x tCK. An example
of a READ latency is shown in Figure 8. An example of
a WRITE latency is shown in Figure 9.
Figure 8: READ Latency
Figure 9: Write Latency
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
AL = 2
ACTIVE n
Burst length = 4
Shown with nominal tAC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
READ n
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
T7
T8
NOP
CL = 3
RL = 5
CAS# latency (CL) = 3
Additive latency (AL) = 2
READ latency (RL) = AL + CL = 5
tRCD (MIN)
NOP
CK
CK#
COMMAND
DQ
DQS, DQS#
ACTIVE n
Burst length = 4
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
T3
T4
T5
NOP
WRITE n
T6
NOP
Din
n + 3
Din
n + 2
Din
n + 1
WL = AL + CL - 1 = 4
T7
NOP
Din
n
CAS# latency (CL) = 3
Additive latency (AL) = 2
WRITE latency = AL + CL -1 = 4
tRCD (MIN)
NOP
AL = 2
CL - 1 = 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT18HTF12872DY-40EA1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 SDRAM DDR II MODUL |
| MT18HTF12872DY-40EB1 | 功能描述:MODULE SDRAM DDR2 1GB 240DIMM RoHS:是 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM |
| MT18HTF12872DY-40ED3 | 功能描述:MODULE DDR2 1GB 240-DIMM RoHS:是 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM |
| MT18HTF12872DY-53EB1 | 功能描述:MODULE SDRAM DDR2 1GB 240DIMM RoHS:是 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM |
| MT18HTF12872DY-53ED3 | 功能描述:MODULE DDR2 1GB 240-DIMM RoHS:是 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM |
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