
512MB, 1GB, 2GB (x72, DR, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
PRELIMINARY
09005aef80e934a6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72DG_A.fm - Rev. A 10/03 EN
21
2003 Micron Technology. Inc.
Table 16:
DDR2 IDD Specifications and Conditions – 2GB
Notes: 1–5; notes appear on
page 25; values shown for DDR2 SDRAM components only
PARAMETER/CONDITION
SYMBOL -53E
-40E
UNITS
Operating one device bank active-precharge current;
tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD0a
TBD
mA
Operating one device bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1a
TBD
mA
Precharge power-down current;
All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING.
IDD2Pb
TBD
mA
Precharge quiet standby current;
All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING.
IDD2Qb
TBD
mA
Precharge standby current;
All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD2Nb
TBD
mA
Active power-down current;
All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
IDD3Pb
TBD
mA
Slow PDN Exit
MR[12] = 1
TBD
mA
Active standby current;
All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD3Nb
TBD
mA
Operating burst write current;
All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4Wa
TBD
mA
Operating burst read current;
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4Ra
TBD
mA
Burst refresh current;
tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
IDD5b
TBD
mA
Self refresh current;
CK and CK# at 0V; CKE
0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING.
IDD6b
TBD
mA
Operating device bank interleave read current;
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x
tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs;
Data bus inputs are SWITCHING; See IDD7 Conditions for detail.
IDD7a
TBD
mA
NOTE:
a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
b - Value calculated reflects all module ranks in this operating condition.