參數(shù)資料
型號(hào): MT18HTF12872DG-40EXX
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: DIMM-240
文件頁數(shù): 22/35頁
文件大小: 717K
代理商: MT18HTF12872DG-40EXX
512MB, 1GB, 2GB (x72, DR, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
PRELIMINARY
09005aef80e934a6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72DG_A.fm - Rev. A 10/03 EN
29
2003 Micron Technology. Inc.
NOTE:
1. Timing and switching specifications for the PLL listed above are critical for proper operation of the DDR2 SDRAM
Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this PLL is available in JEDEC Standard JESD82.
2. Static Phase Offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each
other.
4. Design target is 60ps, unless it is unachievable.
5. VOX spedified at the DRAM clock input, or the test load.
6. The Output Slew Rate is determined from the IBIS model:
Table 22:
PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
PARAMETER
SYMBOL
0°C
TOPR +55°C
VDD = 1.85V ± 0.1V
UNITS
NOTES
MIN
NOMINAL
MAX
Output Enable to any Y/Y#
tEN
––
8
ns
Output Enable to any Y/Y#
tDIS
––
8
ns
Cycle to Cycle Jitter
tJIT
CC
-40
40
ps
Static Phase Offset
t
-50
0
50
ps
Dynamc Phase Offset
tdyn
-50
0
50
ps
Output Clock Skew
tSK
O
––
40
ps
Period Jitter
tJIT
PER
-40
40
ps
Half-Period Jitter
tJIT
HPER
-75
75
ps
Input Clock Slew Rate
tLS
I
1.0
2.5
4
V/ns
Output Clock Slew Rate
tLS
O
1.5
2.5
3
V/ns
Output Differential-Pair Cross-Voltage
VOX
VDDQ/2 - 0.1
VDDQ/2 + 0.1
V
SSC Modulation Frequency
30
33
kHZ
SSC Clock Input Frequency Deviation
0.0
-0.50
%
PLL Loop Bandwidth (-3dB from unity gain)
2.0
MHz
GND
V
DDQ
CU877
V
CK
V
CK
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