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| 型號(hào)： | MSM9225BGA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 32/95頁(yè) |
| 文件大小： | 567K |
| 代理商： | MSM9225BGA-2K |
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MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 25
2.4.5 CAN Bus Timing Register 1 (BTR1: 2Ehex)
This register sets the sampling point used for bus timing.
Writing to the BTR1 bit is enabled, when the INIT bit of the CAN control register (CANC: 0Ehex) is “1”.
The bit configuration is as follows:
MSB
Not
used
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
LSB
BTR1 (2Ehex), R/W: R/W
Initial
value:
00
TSEG13 TSEG12 TSEG11 TSEG10
TSEG1
00
1
× BTL cycle
00
01
2
× BTL cycle
11
10
15
× BTL cycle
11
16
× BTL cycle
TSEG22 TSEG21 TSEG20
TSEG2
00
0
1
× BTL cycle
00
1
2
× BTL cycle
11
0
7
× BTL cycle
11
1
8
× BTL cycle
Unused bit.
Write a “0”.
Figure 2-24 CAN Bus Timing Register 1 (BTR1)
(1) Time segment 1: TSEG13 to TSEG10
This is a 4-bit field to set the sampling point.
Table 2-7 shows the relationship between bit content and TSEG1.
At reset, TSEG13 to TSEG10 are set to “0000”.
Table 2-7 TSEG1 Setting
TSEG13
TSEG12
TSEG11
TSEG10
TSEG1
0
000
1
× BTL cycle
0
001
2
× BTL cycle
1
110
15
× BTL cycle
1
111
16
× BTL cycle
(2) Time segment 2: TSEG22 to TSEG20
This is a 3-bit field to set TSEG2.
Table 2-8 shows the relationship between the bit content and TSEG2.
At reset, TSEG22 to TSEG20 are set to “000”.
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