參數(shù)資料
型號(hào)： MSM9225BGA-2K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 10/95頁
文件大小： 567K
代理商： MSM9225BGA-2K
MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 5
(1) Automatic transmission: ARES
If the automatic transmission of the data frame is used for remote frame reception, set this bit to “1”.
At reset, the ARES bit is set to “0”. The ARES bit is invalid if the message is specified as a group
message.
Notes on Automatic Transmission
Following shows how the transmission is carried out for the messages for which ARES is set to “1” when
a remote frame is received.
The MSM9225B detects the transmission priority of all the messages for which the TRQ (transmission
request) bit is set to “1”, then transmits the messages in sequence from the one with the highest priority.
Note, therefore, that messages for which automatic transmission is set will not always be transmitted
immediately after remote frame reception if there are any other messages to be transmitted.
Also in cases where there are some messages for which TRQ is set to “1”, whereas the TIRS bit of CANC
is not set to “1” because it is not yet desired to transmit them, those messages for which TRQ bit is set to
“1” will be transmitted.
(2) Frame type setting: FRM
This flag sets the frame type of the message to be transmitted/received. A message of a frame type other
than the specified frame type cannot be transmitted/received.
Table 2-2 shows the relationship between setting and frame type.
At reset, the FRM bit is set to “0”.
Table 2-2 Frame Types
Specified as group message
FRM
Transmission frame
Receive frame
0
Data frame
Remote frame
No
1
Remote frame
Data frame
0
Data frame
Yes
1
Transmission not activated
Remote frame
(3) Transmission completion interrupt enable: EIT
This is a flag to enable setting (“1”) the transmission interrupt request flag (ITF) when transmission
completes.
Set this flag from the microcontroller.
The EIT bit is valid when the EINTT bit of the CANI register is “1”. (See Section 2.4.2.)
At reset, the EIT bit is set to “0”.
(4) Receive completion interrupt enable: EIR
This is a flag to enable setting (“1”) the receive interrupt request flag (IRF) when receiving completes.
Set this flag from the microcontroller.
The EIR bit is valid when the EINTR bit of the CANI register is “1”. (See Section 2.4.2.)
At reset, the EIR bit is set to “0”.
(5) Receive status: RCS
When receiving completes, the RCS bit becomes “1”. Write “0” to the RCS bit before the micro-controller
reads receive data. When receiving the remote frame, the RCS bit becomes “1” just after the reception.
When receiving the data frame, it becomes “1” after receive data is written to the message box.
At reset, the RCS bit is set to “0”.
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