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| 型號： | MSM9225BGA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 3/95頁 |
| 文件大?。?/td> | 567K |
| 代理商： | MSM9225BGA-2K |
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MSM9225B User’s Manual
Chapter 1 Overview
1 – 4
1.6
Pin Descriptions
Table 1-1 Pin Description
Symbol
Pin
Type
Description
CS
10
I
Chip select pin. When “L”, PALE, PWR, PRD/SRW, SCLK and SDO pins
(microcontroller interface pins) are valid.
When “H”, these pins are invalid.
A7-0
41-44,
1-4
I
Address bus pins (when using separate buses). If used with a multiplexed bus
or if used in the serial mode, fix these pins at “H” or “L” levels.
AD7-0/
D7-0
31-38
I/O
Multiplexed bus: Address/data pins (AD7-0)
Separate buses: Data pins (D7-0)
If used in the serial mode, fix these pins at a “L” level.
PWR
26
I
Write input pin if used in the parallel mode. Data is captured when this pin is at a
“L” level.
If used in the serial mode, fix this pin at a “L” level.
PRD/
SRW
9I
Parallel mode: Read signal pin (PRD)
When at a “L” level, data is output from the data pins.
Serial mode: Read/write signal pin (SRW)
When at a “H” level, data is output from the SDO pin.
When at a “L” level, the SDO pin is at high impedance, and data is captured
beginning with the second byte of data input from the SDI pin.
PALE
27
I
Address latch signal pin
When at a “H” level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary or in the
serial mode, fix this pin at a “H” or “L” level.
SDI
7
I
Serial data input pin
Addresses (1st byte) and data (beginning from the 2nd byte) are input to this pin,
LSB first. If used in the parallel mode, fix this pin at a “H” or “L” level.
SDO
5
O
Serial data output pin
When the CS pin is at a “H” level, this pin is at high impedance. When CS is at a
“L” level, data is output from this pin, LSB first.
If used in the parallel mode, fix this pin at a “H” or “L” level.
SCLK
8
I
Shift clock input pin for serial data
At the rising edge of the shift clock, SDI pin data is captured. At the falling edge,
data is output from the SDO pin.
PRDY/
SWAIT
16
O
Ready output pin
When required by the MSM9225B, a signal may be output to extend the bus
cycle until the internal access is completed.
Internal access in progress
After completion of access
Parallel mode
(PRDY)
“L” level output
High impedance output
Serial mode
(SWAIT)
“H” level output
“L” level output
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