參數(shù)資料
型號(hào)： MSM7662
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： NTSC/PAL Digital Video Decoder(NTSC/PAL制式數(shù)字視頻譯碼器)
中文描述： NTSC / PAL數(shù)字視頻解碼器（的NTSC / PAL制式數(shù)字視頻譯碼器）
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 369K
代理商： MSM7662
Semiconductor
MSM7662
5/47
PIN DESCRIPTIONS (continued)
Pin
31
32
33
34
35
36
37
38
39
40
Symbol
SCAN
TEST[2]
TEST[1]
TEST[0]
SLEEP
RESET_L
DV
DD
DGND
SCL
SDA
Type
I
I
I
I
I
I
—
—
I
I/O
Description
Test input. Normally fixed at "0" (pulled down by internal resistor).
Test input. Normally fixed at "0" (pulled down by internal resistor).
Test input. Normally fixed at "0" (pulled down by internal resistor).
Test input. Normally fixed at "0" (pulled down by internal resistor).
0: normal operation, 1: sleep operation
Reset input pin (active "L")
Digital power supply
Digital ground
I
2
C-bus clock input
I
2
C-bus data I/O pin
Internal/external sync switching pin (pulled down by internal resistor).
0: Internal sync mode, 1: External sync mode; use external PLL
Clock select input pin (pulled down by internal resistor).
"L": double-speed 27 MHz, "H": normal clock 13.5 MHz
B data output during RGB mode
B[7]: MSB, B[0]: LSB
Digital ground
Digital power supply
ITU-RBT.656 data output during ITU-RBT.656 output mode
ITU-RBT.601 luminance data output during ITU-RBT.601 output mode
G data output during RGB mode, Y[7]: MSB, Y[0]: LSB
Digital power supply
Digital ground
Chroma data output during ITU-RBT.601 output mode
R data output during RGB mode, C[7]: MSB, C[0]: LSB
Field display output
If field is odd, "H" is output
Horizontal valid pixel timing output pin
Vertical valid line timing output pin
V sync output pin
H sync output pin
Pixel clock output
System clock output
Digital ground
Digital power supply
System clock input
Default is internal FIFO overflow detection
(TV, VTR mode switching guide)
0: non-detection, 1: detection
CSYNC output (selected by register)
When PLLSEL external sync mode is selected, HSYNC output
41
PLLSEL
I
42
CLKSEL
I
43 to 50
B[7:0]
I/O
51
52
DGND
DV
DD
—
—
53 to 60
Y[7:0]
O
61
62
DV
DD
DGND
—
—
63 to 70
C[7:0]
I/O
71
ODD/EVEN
O
72
73
74
75
76
77
78
79
80
HVALID
VVALID
VSYNC_L
HSYNC_L
CLKXO
CLKX2O
DGND
DV
DD
CLKX2
O
O
O
O
O
O
—
—
I
81
STATUS[3]
O
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