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Semiconductor
MSM7662
15/47
4. Synchronization Block
This block processes the sync signals. Synchronous signals are generated for chip output and for
internal use. Various signals are output from this block and the following operating modes can
be selected.
1) Adjustment of SYNC threshold level (internal sync)
2) HSY control
2-1) Fine adjustment of HSY signal (start side)
2-2) Fine adjustment of HSY signal (stop side)
3) HSY signal enable selection
High Level*
Active
Low Level
The HSY signal provides the sync-tip-clamp processing for the A/D converter.
4) Fine adjustment of HSYNC_L signal
5) HVALID control
5-1) Fine adjustment of HVALID signal (start side)
5-2) Fine adjustment of HVALID signal (stop side)
6) VVALID control
6-1) Fine adjustment of VVALID signal (start side)
6-2) Fine adjustment of VVALID signal (stop side)
Data signals are transferred at the rising edge of the HVALID signal.
7) FIFO and Field Memory mode selection
FIFO-1 mode*: Sets and outputs a standard value for the number of pixels per 1H from the
internal FIFO.
This mode is also compatible (to a degree) with non-standard VTR signals.
FIFO-2 mode: Sets and outputs a constant pixel number corresponding to the input H
interval for the number of pixels per 1H from the internal FIFO.
FM-1 mode:
This mode outputs the decoded results according to the SYNC signal.
Usage of external field memory is required to manage the number of pixels
and to absorb jitter.
Memory control signals are to be generated externally.
FM-2 mode:
This mode is compatible with considerably distorted non-standard VTR
signals. Jitter is absorbed by using external field memory (2 Mb
¥
2) and the
standard value is set as the pixel number.
Field memory control signals are output simultaneously from M[7:4].
8) Field memory control signals
If the FM-1 mode uses external field memory (2 Mb
¥
2) instead of the internal FIFO, field
memory control signals are supplied from pins M[7:4].