參數(shù)資料
型號(hào)： MSC8254TVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 26/68頁(yè)
文件大?。?/td> 909K
代理商： MSC8254TVT800B
MSC8254 Quad-Core Digital Signal Processor Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
32
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-Ended Mode
— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left
unconnected or tied to ground.
— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.
2.5.3.2
DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The
MSC8254 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The
transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12.
Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 9. Single-Ended Reference Clock Input DC Requirements
SR[1–2]_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SR[1–2]_REF_CLK
400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV
0V
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MSC8256 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Six-Core Digital Signal Processor
MSC8256_11 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Six-Core Digital Signal Processor
MSC8256ETAG1000B 制造商:Freescale Semiconductor 功能描述:DSP,STARCORE, 6-CORE - Bulk
MSC8256SAG1000B 制造商:Freescale Semiconductor 功能描述:DSP,STARCORE,6-CORE R2.1 - Bulk
MSC8256SVT1000B 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DSPStarcore6-core R2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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