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參數(shù)資料
| 型號： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 41/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126VT8000 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Revision History
Freescale Semiconductor
46
7
Revision History
Table 31 provides a revision history for this data sheet.
Table 31. Document Revision History
Revision
Date
Description
0
May 2004
Initial release.
1
Jun. 2004
Updated timing number 32b.
Updated DSI timing specifications.
2
Sep 2004
New orderable parts added with other core voltage and temperature options.
Updated thermal characteristics.
In Table 2-14, removed references to 30 pF.
Design guidelines and layout recommendations updated.
3
Nov. 2004
Added 500 MHz core and 166 MHz bus speed options.
Definitions of GPIO[27–28] updated.
Bus, TDM, and GPIO timing updated. I2C timing changed to GPIO timing.
GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.
Design guidelines update.
4
Jan. 2005
Package type changed to FC-PBGA for all frequencies.
Low-voltage 300 MHz power changed to 1.1 V.
HRESET and SRESET definitions updated.
Undershoot and overshoot values added for VDDH.
RMII timing updated.
Design guidelines updated and reorganized.
5
May 2005
Multiple AC timing specifications updated.
6
May 2005
Multiple AC timing specifications updated.
7
Jul. 2005
Multiple AC timing specifications updated.
8
Jul. 2005
AC specification table layout modified.
9
Sep. 2005
ETHTX_EN type and TRST description updated.
Package drawing updated.
Clock specifications updated.
Start-up sequence updated.
10
Oct 2005
VDDH + 10% changed to VDDH + 8% in Figure 2-1.
VDDH +20% changed to VDDH + 17% in Figure 2-1.
11
Apr 2006
Reset timing updated to reflect actual values in Table 2-11.
12
Oct. 2006
Added new timings 17 and 18 for IRQ set time and pulse width in Table 2-13
13
Dec. 2007
Converted to new data sheet format.
Added PLL supply current to Table 5 in Section 2.4.
Modified Figure 5 in Section 2.4 to make it clear that the time limits for undershoot referred to values
below –0.3 V and not GND.
Added cross-references between Sections 2.5.2 and Section 3.1 and 3.2.
Added power-sequence guidelines to Sections 2.5.2.
Added CLKIN jitter characteristic specifications to Table 9.
Added additional guidelines to prevent reverse current to Section 3.1.
Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.
14
May 2008
15
Dec 2008
Clarified the wording of note 2 in Table 15 on p. 24.
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