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| 型號(hào)： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 1138K |
| 代理商： | MSC8126VT8000 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
28
2.5.6
DSI Timing
The timings in the following sections are based on a 20 pF capacitive load.
2.5.6.1 DSI Asynchronous Mode
Table 18. DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
100
Attributes1 set-up time before strobe (HWBS[n]) assertion
1.5
—
ns
101
Attributes1 hold time after data strobe deassertion
1.3
—
ns
102
Read/Write data strobe deassertion width:
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
1.8 + TREFCLK
5 + TREFCLK
5 + (1.5
× TREFCLK)
5 + (2.5
× TREFCLK)
1.8 + TREFCLK
—
ns
103
Read data strobe deassertion to output data high impedance
—
8.5
ns
104
Read data strobe assertion to output data active from high impedance
2.0
—
ns
105
Output data hold time after read data strobe deassertion
2.2
—
ns
106
Read/Write data strobe assertion to HTA active from high impedance
2.2
—
ns
107
Output data valid to HTA assertion
3.2
—
ns
108
Read/Write data strobe assertion to HTA valid2
1.1 V core
1.2 V core
—
7.4
6.7
ns
109
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
—6.5
ns
110
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
—6.5
ns
111
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
—
5 + TREFCLK
5 + (1.5
× TREFCLK)
5 + (2.5
× TREFCLK)
ns
112
Read/Write data strobe assertion width
1.8 + TREFCLK
—ns
201
Host data input set-up time before write data strobe deassertion
1.0
—
ns
202
Host data input hold time after write data strobe deassertion
1.1 V core
1.2 V core
1.7
1.5
—
ns
Notes:
1.
Attributes refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2.
This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3.
All values listed in this table are tested or guaranteed by design.
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