參數(shù)資料
型號(hào)： MSC8126VT8000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 500 MHz, OTHER DSP, PBGA431
封裝： 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431
文件頁(yè)數(shù)： 10/48頁(yè)
文件大小： 1138K
代理商： MSC8126VT8000
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
18
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
1.
During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
2.5.3
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum
frequency values are not exceeded.
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
400/500
Reference frequency (REFCLK)
133/166
Internal bus frequency (BLCK)
133/166
DSI clock frequency (HCLKIN)
HCLKIN
≤ (min{100 MHz, CLKOUT})
External clock frequency (CLKIN or CLKOUT)
133/166
Table 8. Clock Frequencies
Characteristics
Symbol
400 MHz Device
500 MHz Device
Min
Max
Min
Max
CLKIN frequency
FCLKIN
20
133.3
20
166.7
BCLK frequency
FBCLK
40
133.3
40
166.7
Reference clock (REFCLK) frequency
FREFCLK
40
133.3
40
166.7
Output clock (CLKOUT) frequency
FCLKOUT
40
133.3
40
166.7
SC140 core clock frequency
FCORE
200
400
200
500
Note:
The rise and fall time of external clocks should be 5 ns maximum
3.3 V
1.2 V
A
B
VDD/VCCSYN
VDDH (IO)
t (time)
V
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