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| 型號(hào)： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁(yè)數(shù)： | 31/48頁(yè) |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126VT8000 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
37
2.5.12
EE Signals
2.5.13
JTAG Signals
Figure 27. GPIO Timing
Table 29. EE Pin Timing
Number
Characteristics
Type
Min
65
EE0 (input)
Asynchronous
4 core clock periods
66
EE1 (output)
Synchronous to Core clock
1 core clock period
Notes:
1.
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2.
Refer to Table 1-4 on page 1-6 for details on EE pin functionality.
Figure 28. EE Pin Timing
Table 30. JTAG Timing
No.
Characteristics
All
frequencies
Unit
Min
Max
700
TCK frequency of operation (1/(T
C ×
4); maximum 25 MHz)
0.0
25
MHz
701
TCK cycle time
40.0
—
ns
702
TCK clock pulse width measured at VM = 1.6 V
High
Low
20.0
16.0
—
ns
703
TCK rise and fall times
0.0
3.0
ns
REFCLK
GPIO
(Output)
GPIO
(Input)
Valid
603
High Impedance
604
605
602
601
EE1 out
EE0 in
65
66
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