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參數(shù)資料
| 型號(hào)： | MSC8126VT8000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, 500 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126VT8000 |
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MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
22
2.5.5
System Bus Access Timing
2.5.5.1
Core Data Transfers
Generally, all MSC8126 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The
REFCLK is the CLKIN signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle
is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling
edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows.
Table 13. Tick Spacing for Memory Controller Signals
BCLK/SC140 clock
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T2
T3
T4
1:4, 1:6, 1:8, 1:10
1/4 REFCLK
1/2 REFCLK
3/4 REFCLK
1:3
1/6 REFCLK
1/2 REFCLK
4/6 REFCLK
1:5
2/10 REFCLK
1/2 REFCLK
7/10 REFCLK
Figure 10. Internal Tick Spacing for Memory Controller Signals
REFCLK
T1
T2
T3
T4
REFCLK
T1
T2
T3
T4
for 1:3
for 1:5
REFCLK
T1
T2
T3
T4
for 1:4, 1:6, 1:8, 1:10
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