參數(shù)資料
型號(hào)： MSC8126VT8000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 500 MHz, OTHER DSP, PBGA431
封裝： 20 X 20 MM, LEAD FREE, PLASTIC, FCBGA-431
文件頁(yè)數(shù)： 17/48頁(yè)
文件大?。?/td> 1138K
代理商： MSC8126VT8000
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
24
31
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK
rising edge
4.9
5.8
ns
32a
Address bus max delay from the 50% level of the REFCLK rising
edge
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
5.5
4.2
5.5
3.9
6.4
5.1
ns
32b
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50%
level of the REFCLK rising edge
5.1
6.0
ns
32c
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
5.7
6.6
ns
32d
BADDR max delay from the 50% level of the REFCLK rising edge
4.2
5.1
ns
33a
Data bus max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
3.9
6.1
3.7
6.1
4.8
7.0
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
5.3
6.5
5.3
6.5
6.2
7.4
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50%
level of the REFCLK rising edge
4.2
3.9
5.1
ns
35a
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK
rising edge
4.7
5.6
ns
35b
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the
REFCLK rising edge
4.5
5.4
ns
Notes:
1.
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
3.
The maximum bus frequency depends on the mode:
4.
In 60x-compatible mode connected to another MSC8126 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8126.
To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8122 Reference Manual for details.
Table 15. AC Timing for SIU Outputs (continued)
No.
Characteristic
Value for Bus Speed in MHz
Units
Ref = CLKIN
Ref = CLKOUT
133
166
133
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