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參數(shù)資料
| 型號(hào)： | MQ80C52XXX-36/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 7/152頁(yè) |
| 文件大?。?/td> | 2528K |
| 代理商： | MQ80C52XXX-36/883 |
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104
2486AA–AVR–02/2013
ATmega8(L)
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
46 shows a block diagram of the counter and its surrounding environment.
Figure 46. Counter Unit Block Diagram
Signal description (internal signals):
count
Increment or decrement TCNT2 by 1
direction
Selects between increment and decrement
clear
Clear TCNT2 (set all bits to zero)
clk
T2
Timer/Counter clock
TOP
Signalizes that TCNT2 has reached maximum value
BOTTOM
Signalizes that TCNT2 has reached minimum value (zero)
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
T2). clkT2 can be generated from an external or internal clock source,
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
T2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare Output
OC2. For more details about advanced counting sequences and waveform generation, see
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int. Req.)
TOP
BOTTOM
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk
Tn
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