參數(shù)資料
型號: MQ80C52XXX-36/883
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
封裝: CERAMIC, QFP-44
文件頁數(shù): 132/152頁
文件大?。?/td> 2528K
代理商: MQ80C52XXX-36/883
42
ATmega8535(L)
2502K–AVR–10/06
Figure 21. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8535 and will always read as zero.
Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See
Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
Table 17. WDT Configuration as a Function of the Fuse Settings of S8538C and
WDTON
S8535C
WDTON
Safety
Level
WDT Initial
State
How to Disable
the WDT
How to
Change
Time-out
Unprogrammed
1
Disabled
Timed
sequence
Timed
sequence
Unprogrammed
Programmed
2
Enabled
Always enabled
Timed
sequence
Programmed
Unprogrammed
0
Disabled
Timed
sequence
No
restriction
Programmed
2
Enabled
Always enabled
Timed
sequence
WATCHDOG
OSCILLATOR
Bit
7654
321
0
WDCE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R/W
Initial Value
0000
000
0
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