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參數(shù)資料
| 型號(hào)： | MQ80C52XXX-36/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 55/152頁(yè) |
| 文件大小： | 2528K |
| 代理商： | MQ80C52XXX-36/883 |
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148
2486AA–AVR–02/2013
ATmega8(L)
USART Register
Description
USART I/O Data
Register – UDR
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDR Register location. Reading the
UDR Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-bit, 6-bit, or 7-bit characters the upper unused bits will be ignored by the Transmitter and
set to zero by the Receiver.
The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data
written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When
data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the
data into the Transmit Shift Register when the Shift Register is empty. Then the data will be seri-
ally transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-
Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.
USART Control and
Status Register A –
UCSRA
Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXC bit will become zero. The RXC Flag can
be used to generate a Receive Complete interrupt (see description of the “Bit 7 – RXCIE: RX
Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDR). The TXC Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see descrip-
Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is
one, the buffer is empty, and therefore ready to be written. The UDRE Flag can generate a Data
Register Empty interrupt (see description of the “Bit 5 – UDRIE: USART Data Register Empty
UDRE is set after a reset to indicate that the Transmitter is ready.
Bit
76543210
RXB[7:0]
UDR (Read)
TXB[7:0]
UDR (Write)
Read/Write
R/W
Initial Value
00000000
Bit
765
4321
0
RXC
TXC
UDRE
FE
DOR
PE
U2X
MPCM
UCSRA
Read/Write
R
R/W
R
R/W
Initial Value
001
0000
0
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