參數(shù)資料
型號: MQ80C52XXX-36/883
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
封裝: CERAMIC, QFP-44
文件頁數(shù): 147/152頁
文件大小: 2528K
代理商: MQ80C52XXX-36/883
92
8151H–AVR–02/11
ATmega128A
13.1.3
EIMSK - External Interrupt Mask Register
Bits 7:0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-
rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger
an interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
13.1.4
EIFR - External Interrupt Flag Register
Bits 7:0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep
mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input
Bit
765
4321
0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
IINT0
EIMSK
Read/Write
R/W
Initial Value
000
0000
0
Bit
765
4321
0
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
IINTF0
EIFR
Read/Write
R/W
Initial Value
000
0000
0
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