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參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
14
Freescale Semiconductor
MPC9894
Input and Feedback Divider Configuration Register
The Input and Feedback Divider Configuration Register is
used to select the input divider value and the feedback divider
values. The four bits for Input_FB_Div allow 16 combinations
of input and feedback divider ratios. Some input and output
frequency ranges may overlap allowing a choice of PLL
closed loop bandwidths. This selection may be useful when
PLL devices are cascaded.
Device Status Register
The Device Status Register contains a copy of the status
SEL_STAT[1:0], LOCK and CLK_STAT[3:0] pins. In addition,
bit 7 is an INT flag bit, which is used to indicate a setting of a
bit in the CLK_STAT[3:0], a clearing of the LOCK bit and a
change in the value of the SEL_STAT[1:0] bits.
The CLK_STAT[3:0] bits are sticky and remain set until
manually reset through the Mode Configuration Register.
The setting of the register INT bit is reflected on the
interrupt pin only if interrupts are enabled. Enabling interrupts
is done by the setting of the INT_E bit which is located in the
Device Configuration Register. Reading of the Status
Register clears the INT flag.
Table 22. Input and Feedback Divider Configuration Register (Register 4 — Read/Write)
Bit
76543210
Description
Reserved
Input_FB_Div[3:0]
Reset default
n/a
0000
Preset default
n/a
0011
Table 23. Input_FB_Div[3:0]
Input_FB_Div[3:0]
Input Divider (P)
Feedback Divider (M)
0000
1
16
0001
1
12
0010
2
12
0011
1
8
0100
2
16
0101
reserved
0110
2
8
0111
3
12
1000
4
16
1001
reserved
1010
4
12
1011
reserved
1100
reserved
1101
reserved
1110
4
8
1111
6
12
Table 24. Status Register (Register 5 — Read Only)
Bit
7
6
543
2
1
0
Description INT
Inverse of INT
signal
CLK_STAT[3:0]
Status of CLK3, CLK2, CLK1 and CLK0 (sticky)
Copy of CLK_STAT[3:0] signal
LOCK
Inverse of LOCK
signal
SEL_STAT[1:0]
Copy of SEL_STAT[1:0] signal
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