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參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC9894
Control Inputs and Outputs
EX_FB_SEL
Input
LVCMOS Selects between external feedback and internal feedback
VDD
high
CLK_VALID[3:0](1)
Input
LVCMOS Validates the clock inputs CLK0 to CLK3 (internal pullup)
VDD
high
CLK_ALARM_RST
Input
LVCMOS Reset of all four alarm status flags and clock selection status flag
(internal pullup)
VDD
low
PLL_BYPASS
Input
LVCMOS Select static test mode (internal pulldown)
VDD
high
MEDIA
Input
LVCMOS Output impedance control
VDD
high
MR
Input
LVCMOS Device reset (internal pullup)
VDD
low
LOCK
Output
LVCMOS PLL lock indicator
VDD
low
CLK_STAT[3:0]
Output
LVCMOS Clock input status indicator
VDD
high
SEL_STAT[1:0]
Output
LVCMOS Reference clock selection indicator
VDD
high
BUSY
Output
LVCMOS IDCS switching activity indicator
VDD
low
MBOOT
Input
LVCMOS Activates I2C boot sequence (internal pulldown)
VDD
high
PRESET
Input
LVCMOS Enables Preset configuration of configuration registers on release of
MR
(internal pulldown)
VDD
high
INT
Output
OD
Indicate any status IDCS change
VDD
low
MSTROUT_EN
Input
LVCMOS Master Enable for all Outputs (internal pulldown)
VDD
high
SEL_2P5V
Input
LVCMOS Device core power supply selection for VDD and VDDA
VDD
high
I2C Interface
SCL
I/O
OD
I2C interface control, clock
VDD
—
SDA
I/O
OD
I2C interface control, data
VDD
—
ADDR[2:0]
Input
LVCMOS I2C interface address lines (10K pullup)
VDD
high
IEEE 1149.1 and Test
TMS
Input
LVCMOS JTAG test mode select (10K pullup)
VDDIC
—
TDI
Input
LVCMOS JTAG test data input (10K pullup)
VDDIC
—
TDO
Output
LVCMOS JTAG test data output
VDDIC
—
TCK
Input
LVCMOS JTAG test clock
VDDIC
—
TRST
Input
LVCMOS JTAG test reset (10K pullup)
VDDIC
—
PLL_TEST[2:0]
Input
LVCMOS PLL_TEST pins (factory use only, MUST BE CONNECTED TO GND)
N/A
—
TPA
Output
LVCMOS PLL Analog test pin (factory use only, LEAVE OPEN)
VDDA
—
Power and Ground
GND
Supply
Ground
Negative power supply
—
VDD
Supply
—
Positive power supply for the device core, output status and control
inputs. (3.3 V or 2.5 V)
—
VDDAB
Supply
—
Supply voltage for output banks A and B (QA0 through QB1)
(3.3 V or 2.5 V)
—
VDDCD
Supply
—
Supply voltage for output banks C and D (QC0 through QD1) and QFB
(3.3 V or 2.5 V)
—
VDDIC
Supply
—
Supply voltage for differential inputs clock inputs CLK0 to CLK3 and
FB_IN (3.3 V or 2.5 V)
—
—-
VDDA
Supply
—
Clean supply for analog portions of the PLL (This voltage is derived via
a RC filter from the VDD supply)
—
1. bit order = msb to lsb.
Table 1. Pin Configurations (Continued)
Pin
I/O
Type
Function
Supply
Active State
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC990F18 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC991 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC991FA | 制造商:Motorola Inc 功能描述: |
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