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參數資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數： | 13/28頁 |
| 文件大小： | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
20
Freescale Semiconductor
MPC9894
Table 39. AC Characteristics (TJ = –40°C to +110°C)(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VDD = 3.3 V ±5%, VDDAB,CD,IC = 3.3 V ±5% or VDDAB,CD,IC = 2.5 V ±5%
Input and output timing specification
fREF
Input reference frequency
Input reference frequency in PLL bypass mode(3)
21.25
28.33
56.66
42.5
85.0
113.32
170
42.5
56.67
113.34
85
170
226.68
340
MHz
Input_FB_Div[3:0] = 0
Input_FB_Div[3:0] = 1
Input_FB_Div[3:0] = 2
Input_FB_Div[3:0] = 3,4
Input_FB_Div[3:0] = 6,7,8
Input_FB_Div[3:0] = 10
Input_FB_Div[3:0] = 14,15
PLL bypass
fVCO
VCO frequency range(4)
340
680
MHz
fMAX
Output Frequency
÷2 output
÷4 output
÷8 output
÷16 output
170.0
85.0
42.5
21.25
340.0
170.0
85.0
42.5
MHz
PLL locked
fREFDC
Reference Input Duty Cycle
40
60
%
fREFacc
Input Frequency Accuracy(5)
5000
ppm
mae()
Misaligned Edge Specification
±600
±1600
ps
tr, tf
Output Rise/Fall Time
800
ps
20% to 80%
DC
Output duty cycle
47.5
50
52.5
%
fI2C
I2C frequency range
400
kHz
Differential input and output voltages
VPP
Differential input voltage(6) (peak-to-peak) (PECL)
1.3
V
VPP, OK
Differential input voltage(7) (peak-to-peak) (PECL)
0.3
V
VPP, NOK
Differential input voltage(8) (peak-to-peak) (PECL)
0.1
V
VO(P-P)
Differential output voltage (peak-to-peak) (PECL)
0.3
0.8
V
PLL and IDCS specifications
t()
Propagation Delay (static phase offset)
CLKX, CLKX to FB_IN, FB_IN
–100
150
ps
PLL locked with external
feedback selected
tsk(O)
Output-to-output Skew within a bank(9)
Output-to-output Skew across a bank(9)
50
100
ps
PER/CYC
Rate of change of period(10)
÷2 output
÷4 output
÷8 output
÷16 output
+40
+80
+120
+160
ps
slew_control = 1
PER/CYC
Rate of change of period(11)
÷2 output
÷4 output
÷8 output
÷16 output
±40
±80
±120
±160
ps
slew_control = 0
Jitter and bandwidth specifications
tJIT(CC)
Cycle-to-cycle jitter
RMS (1
σ)
10
ps
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
15
ps
N = 16, 16, 16, 16
tJIT(PER)
Period Jitter
RMS (1
σ)
10
ps
N = 2, 2, 2, 2
N = 4, 4, 4, 4
N = 8, 8, 8, 8
15
ps
N = 16, 16, 16, 16
tJIT()
I/O Phase Jitter
RMS (1
σ)30
ps
BW
PLL closed loop bandwidth(12)
2MHz
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