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參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
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Advanced Clock Drivers Devices
6
Freescale Semiconductor
MPC9894
DEVICE CONFIGURATION
I2C Configuration and I2C Addressing
The MPC9894 is configured via a series of 8-bit registers.
The bits in these registers allow a wide range of control over
the operation of the MPC9894 clock generator. These
registers are accessed via an I2C interface through which a
7-bit address is sent from the I2C master to select the specific
I2C slave device being accessed. The address for this clock
driver is found in the first of the MPC9894 I2C registers. The
format of this address has a fixed most-significant four bits of
binary 1101 while the least-significant 3 address bits are read
from the 3 ADDR pins. This provides the capability to
configure up to 8 clock devices on a single I2C interface.
In addition, activation of the MBOOT pin on power-up or
reset initiates an automatic boot sequence allowing the clock
generators to be initialized from an I2C compatible EEPROM.
In this case the MPC9894 becomes an I2C master and the
configuration bits are filled by the information from the first 6
bytes of the EEPROM. This allows the clock to be configured
without a controlling I2C bus master if desired. The PRESET
pin allows the device to be configured without a I2C bus
master.
The detailed register descriptions are found in the section,
I2C Interface and configuration/status register.
IDCS MODE Configuration
Three register bits are used to configure the MPC9894 in
either an automatic clock switch mode or into a manual clock
select mode. The three mode select bits are defined in
IDCS modes 000 through 011 allow manual selection
between the four clock sources. IDCS modes 100 through
111 enable the automatic mode of the IDCS.
Automatic IDCS Mode
In the automatic mode, the clock failure detection is
enabled and the IDCS overwrites the selected clock on a
clock failure. The IDCS operation requires PLL_BYPASS = 0
and IDCS_MODE[2] = 1. The reference clock is handled in a
round robin method based upon clock validity and the
qualification input CLK_VALID[3:0]: The qualification input is
obtained from the four input pins, CLK_VALID[3:0]. If any of
the CLK_VALID pins are low the associated clock input will
be considered “unqualified” and thus not selected as a
reference clock. Alternatively, if a clock input does not have a
valid clock signal, it will not be selected and the next qualified
and valid clock is selected as the reference clock.
For example, if IDCS_MODE[2:0] = 100 (the IDCS is in
automatic mode), CLK_VALID[3:0] = 1111 and CLK0, CLK1,
CLK2, and CLK3 have valid input clock signals then CLK0 is
the primary clock and CLK1 is the secondary clock. The IDCS
selects the primary clock as the reference clock and the PLL
will phase-lock the clock outputs to the CLK0 input. Upon the
failure of CLK0 the IDCS will select CLK1 as the reference
clock and initiate a switch, making CLK1 the reference clock
and CLK2 the secondary clock. If CLK1 fails, the IDCS will
switch to CLK2, etc.
A de-asserted CLK_VALID[] pin disables the associated
clock input as secondary clock. The associated clock input
cannot be selected by the IDCS as secondary clock signal.
For instance, if CLK0 is the primary clock and
CLK_VALID[3:0] = 1101, the IDCS will select CLK2 upon a
clock failure of CLK0 (CLK1 is disabled by the CLK_VALID1
input, allowing external logic to control the IDCS switch logic).
If a clock is the reference clock signal and its associated
CLK_VALID signal is switched from ‘valid' to ‘invalid', the
IDCS initiates a clock input switch, selecting the next
available clock input (secondary clock).
An invalid clock(1) signal triggers the associated clock
status output (CLK_STAT[3:0]), independent of the primary
and reference clock. These pins go set on a clock failure and
remain set (sticky) until the CLK_ALARM_RST pin or the
individual alarm reset bits (ALARM_RST[3:0]) are asserted.
The CLK_STAT[3:0] outputs are mirrored in the device
register 4 for I2C bus access.
After each successful IDCS-commanded switch, the
primary clock as set by IDCS_MODE[1xx] is no longer the
reference clock. The user may reset the IDCS flags by
asserting the individual ALARM_RST[3:0] bits after each
IDCS-commanded switch. Activation of ALARM_RST[3:0]
does not change the reference clock. A user-commanded
change of the primary clock in automatic mode requires a
write command to the IDCS_MODE[2:0] = 0xx bits (the
primary clock and SEL_STAT[1:0] can be freely changed by
setting IDCS_MODE[2:0] = 1xx). If the reference clock is not
the primary clock, a write command to IDCS_MODE[2:0] =
1xx will cause the PLL to lock on the primary clock, given the
new primary clock is a qualified clock.
Table 3. MPC9894 IDCS Configuration
IDCS_MODE [2:0]
Description
Primary Clock
Secondary Clock(1)
1. For CLK_VALID[3:0] = 1111 and input clock validity.
Tertiary Clock
Quaternary Clock
000
Manual
CLK0
n/a
001
CLK1
n/a
010
CLK2
n/a
011
CLK3
n/a
100
Automatic
CLK0
CLK1
CLK2
CLK3
101
CLK1
CLK2
CLK3
CLK0
110
CLK2
CLK3
CLK0
CLK1
111
CLK3
CLK0
CLK1
CLK2
1. See Clock Failure Detection.
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