- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26839 > MPC9894VFR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 PDF資料下載
參數(shù)資料
| 型號： | MPC9894VFR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| 封裝： | 11 X 11 MM, MAPBGA-100 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 362K |
| 代理商： | MPC9894VFR2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Advanced Clock Drivers Devices
Freescale Semiconductor
21
MPC9894
VDD = 3.3 V ±5%, VDDAB,CD,IC = 3.3 V ±5% or VDDAB,CD,IC = 2.5 V ±5%
MR
and PLL Lock
tLOCK
Maximum PLL Lock Time
10
s
treset_ref
MR
hold time on power up
2
ps
treset_pulse
MR
hold time
100
ns
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to VTT.
3. In bypass mode, the MPC9894 divides the input reference clock.
4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF =(fVCO ÷ M) N.
5. All Input Clock frequencies must be within this value to guarantee smooth phase transition on input clock switch.
6. VPP is the minimum differential input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.
7. VPP, OK is the minimum differential input voltage swing required for a valid clock signal. Above VPP, OK the input will be detected as a good
clock (see IDCS).
8. VPP, NOK is the maximum differential input voltage swing for a guaranteed bad clock. Below VPP, NOK the input will be detected as a failed
clock (see IDCS).
9. VDDAB =VDDCD
10. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.
11. Rate of period change is the maximum change of the clock output signal period T per cycle on a IDCS commanded switch.
12. –3 dB point of PLL transfer characteristics.
Table 39. AC Characteristics (TJ = –40°C to +110°C)(1) (2) (Continued)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Z=50
RT = 50
VTT
DUT MPC9894
Z=50
Differential
Pulse Generator
Z=50
RT = 50
VTT
Figure 7. MPC9894 AC Test Reference (Media = 0)
Figure 8 . MPC9894 AC Test Reference (Media = 1)
Z=50
RT = 100
DUT MPC9894
Z=50
Differential
Pulse Generator
Z=50
RT = 50
VTT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC998FAR2 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC998FA | 998 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9990FAR2 | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC9991FAR2 | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC99J93FAR2 | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC990F18 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC991 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC991FA | 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。