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參數(shù)資料
| 型號： | MPC9608FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MPC9608FAR2 |
MPC9608
TIMING SOLUTIONS
9
Figure 9. Output-to-output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference in propa-
gation delay between any similar delay path within a single device.
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CCLK
FB_IN
Figure 10. Propagation delay (tPD, static phase offset)
test reference
The time from the PLL controlled edge to the non controlled edge, di-
vided by the time between PLL controlled edges, expressed as a per-
centage.
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 11. Output Duty Cycle (DC)
Figure 12. I/O Jitter
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles.
TJIT() = |T0 - T1 mean|
CCLK
FB_IN
Figure 13. Cycle-to-cycle Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs.
TN
TJIT(CC) = |TN -TN + 1|
TN + 1
Figure 14. Period Jitter
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles.
TJIT(PER) = |TN - 1/f0|
T0
Figure 15. Output Transition Time Test Reference
tF
tR
VCC =3.3 V
2.4
0.55
Figure 16. Setup and Hold Time (ts, tH) Test Reference
VCC
GND
ts
CCLK
CLK_STOP
VCC
GND
tH
VCC ÷ 2
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