參數(shù)資料
型號(hào): MPC9608FAR2
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, LQFP-32
文件頁(yè)數(shù): 1/12頁(yè)
文件大小: 239K
代理商: MPC9608FAR2
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 2004
Order this document
by MPC9608
1:10 LVCMOS Zero Delay
Clock Buffer
The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a
very wide frequency range and low output skews the MPC9608 is targeted for
high performance and mid-range clock tree designs.
Features
1:10 outputs LVCMOS zero-delay buffer
Single 3.3 V supply
Supports a clock I/O frequency range of 12.5 to 200 MHz
Selectable divide-by-two for one output bank
Synchronous output enable control (CLK_STOP)
Output tristate control (output high impedance)
PLL bypass mode for low frequency system test purpose
Supports networking, telecommunications and computer applications
Supports a variety of microprocessors and controllers
Compatible to PowerQuicc I and II
Ambient Temperature Range -40
°C to +85°C
32-lead Pb-free package available
Functional Description
The MPC9608 uses an internal PLL and an external feedback path to lock its
low-skew clock output phase to the reference clock phase, providing virtually zero
propagation delay. This enables nested clock designs with near-zero insertion
delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed
from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input
frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs
to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-
chronized to the input reference for both bank B configurations.
Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,
the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides
a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification
do not apply.
CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL
losing lock.
The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-
nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines on the inci-
dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A
MPC9608
LOW VOLTAGE 3.3 V
LVCMOS 1:10 ZERO-DELAY
CLOCK BUFFER
AC SUFFIX
32 LEAD LQFP PACKAGE-Pb-free
CASE 873A
REV 2
相關(guān)PDF資料
PDF描述
MPC9608AC PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CFAR2 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CFA 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CAC 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC961CFA MPC900 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC961C 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE ZERO DELAY BUFFER
MPC961CAC 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
MPC961CACR2 功能描述:IC BUFFER ZD 1:18 PLL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器,扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP(8x8) 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
MPC961CFA 功能描述:IC ZDB CMOS LV 1:18 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
MPC961PAC 功能描述:時(shí)鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel