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參數(shù)資料
| 型號： | MPC9608FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MPC9608FAR2 |
MPC9608
8
TIMING SOLUTIONS
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 7 “Optimized Dual Line Termination” should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 6. Single versus Dual Waveforms
TIME (nS)
V
O
LTA
G
E
(V
)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Figure 7. Optimized Dual Line Termination
14
MPC9608
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
Figure 8. CCLK MPC9608 AC test reference for VCC = 3.3 V
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC9608 DUT
VTT
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