參數(shù)資料
型號(hào): MPC961CAC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: PLASTIC, LQFP-32
文件頁(yè)數(shù): 1/11頁(yè)
文件大?。?/td> 736K
代理商: MPC961CAC
DATA SHEET
MPC961C REVISION 5 AUGUST 17, 2009
1
2009 Integrated Device Technology, Inc.
Low Voltage Zero Delay Buffer
MPC961C
The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay buffer. With output
frequencies of up to 200 MHz, output skews of 150 ps the device meets the needs of the most
demanding clock tree applications.
Features
Fully Integrated PLL
Up to 200 MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVCMOS Reference Clock Options
LQFP Packaging
32-lead Pb-free Package Available
±50 ps Cycle-Cycle Jitter
150 ps Output Skews
Functional Description
The MPC961 is offered with two different input configurations. The MPC961C offers an
LVCMOS reference clock while the MPC961P offers an LVPECL reference clock.
When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance
state. Because the OE pin does not affect the QFB output, down stream clocks can be disabled
without the internal PLL losing lock.
The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS compatible
levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50
transmission lines. For series terminated
lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is packaged in a 32-lead LQFP.
Figure 1. MPC961C Logic Diagram
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
CCLK
FB_IN
Q0
Q14
QFB
O
PLL
1
F_RANGE
OE
Q1
Q2
Q3
Q15
Q16
Ref
FB
100 – 200 MHz
50– 100 MHz
The MPC961C requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details.
50 k
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