參數(shù)資料
型號: MPC8569VTANKGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 71/126頁
文件大?。?/td> 2847K
代理商: MPC8569VTANKGB
DDR2 and DDR3 SDRAM Controller
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
49
The following figure shows the DDR2 and DDR3 SDRAM interface input timing diagram.
Figure 8. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
Tolerated Skew for MDQS—MDQ/MECC
tDISKEW
——
ps
2
800 MHz data rate
–425
425
2
667 MHz data rate
–510
510
2
533 MHz data rate
–635
635
2
400 MHz data rate
–885
885
2
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
3. Parameters tested in DDR2 mode are to 400, 533, 667, and 800 MHz data rates and in DDR3 mode to 667 and 800 MHz data
rates.
Table 19. DDR2 and DDR3 SDRAM Interface Input AC Timing Specifications3 (continued)
At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3
Parameter
Symbol
Min
Max
Unit
Note
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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