參數(shù)資料
型號: MPC8569VTANKGB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù): 21/126頁
文件大?。?/td> 2847K
代理商: MPC8569VTANKGB
UTOPIA/POS Interface
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
117
The following figure provides the AC test load for the UTOPIA/POS.
Figure 70. UTOPIA/POS AC Test Load
Figure 71 and Figure 72 represent the AC timing from Table 80. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
The following figure shows the UTOPIA/POS timing with external clock.
Figure 71. UTOPIA/POS AC Timing (External Clock) Diagram
UTOPIA/POS inputs—External clock input setup time
tUEIVKH
4.0
ns
UTOPIA/POS inputs—Internal clock input hold time
tUIIXKH
0—
ns
UTOPIA/POS inputs—External clock input hold time
tUEIXKH
1.2
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are
measured at the pin.
2. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA/POS
outputs internal timing (UI) for the time tUtopia memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 80. UTOPIA/POS AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
UTOPIACLK (Input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
UTOPIA
Output Signals:
UTOPIA
tUEKHOX
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