參數(shù)資料
型號(hào)： MPC8569VTANKGB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 101/126頁
文件大小： 2847K
代理商： MPC8569VTANKGB
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
HDLC, BISYNC, Transparent, and Synchronous UART Interfaces
Freescale Semiconductor
76
2.8.2
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
The following table provides the input and output AC timing specifications for the HDLC, BISYNC, and Transparent protocols.
The following table provides the input and output AC timing specifications for the synchronous UART protocols.
Table 44. HDLC, BISYNC, and Transparent AC Timing Specifications
For recommended operating conditions, see Table 3
Characteristic
Symbol1
Min
Max
Unit
Notes
Outputs—Internal clock delay
tHIKHOV
05.5
ns
2
Outputs—External clock delay
tHEKHOV
18.4
ns
2
Outputs—Internal clock high Impedance
tHIKHOX
05.5
ns
2
Outputs—External clock high Impedance
tHEKHOX
18
ns
2
Inputs—Internal clock input setup time
tHIIVKH
6—
ns
—
Inputs—External clock input setup time
tHEIVKH
4—
ns
—
Inputs—Internal clock input hold time
tHIIXKH
0—
ns
—
Inputs—External clock input hold time
tHEIXKH
1.3
—
ns
—
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal
timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
Table 45. Synchronous UART AC Timing Specifications
For recommended operating conditions, see Table 3
Characteristic
Symbol1
Min
Max
Unit
Notes
Outputs—Internal clock delay
tHIKHOV
011
ns
2
Outputs—External clock delay
tHEKHOV
114
ns
2
Outputs—Internal clock high Impedance
tHIKHOX
011
ns
2
Outputs—External clock high Impedance
tHEKHOX
114
ns
2
Inputs—Internal clock input setup time
tHIIVKH
10
—
ns
—
Inputs—External clock input setup time
tHEIVKH
8—
ns
—
Inputs—Internal clock input hold time
tHIIXKH
0—
ns
—
Inputs—External clock input hold time
tHEIXKH
1—
ns
—
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal
timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
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