Communication Processor Module
16-342
MPC823 USER’S MANUAL
MOTOROLA
USB
COMMUNICATION
16
PROCESSOR
MODULE
33. Set the PSMR–SCC2 Ethernet to 0x0A0A to configure 32-bit CRC, promiscuous mode
and begin searching for the start frame delimiter 22 bits after RENA.
34. Enable the TENA pin (RTS). Since the MODE field of the GSMR_L is written to
Ethernet, the TENA signal is low. Write PCPAR bit 14 with a one and PCDIR bit 14
with a zero.
35. Write 0x1088003C to the GSMR_L register to enable the SCC2 transmitter and
receiver. This additional write ensures that the ENT and ENR bits are enabled last.
16.10 UNIVERSAL SERIAL BUS CONTROLLER
The universal serial bus (USB) is an industry standard extension to the PC architecture. The
USB controller allows the MPC823 to exchange data with a PC host. It supports data
exchanges between a host computer and a wide range of simultaneously accessible
peripherals. The attached peripherals share USB bandwidth through a host scheduled
token-based protocol. The USB physical interconnect is a tiered star topology. A hub is at
the center of each star. Each wire segment is a point-to-point connection between the host
and a hub or function or a hub connected to another hub/function. There is only one host in
any USB system. The USB transfers signal and power over a four-wire cable. The signalling
occurs over two wires and point-to-point segments. The USB full-speed signalling bit rate is
12Mbps. A limited capability low-speed signalling mode is also defined at 1.5Mbps.
The MPC823 USB controller consists of a transmitter module, receiver module, and two
protocol state machines. The protocol state machines control the receiver and transmitter
modules. One state machine implements the function state diagram and the other
implements the host state diagram. The MPC823 USB controller is capable of implementing
a USB function endpoint, a USB host, or both for testing purposes (loop-back diagnostics).
For USB implementation, it is recommended that you get a copy of the USB Specification
The USB transmitter contains four independent FIFOs, each containing 16 bytes. There is
a dedicated FIFO for each of the four supported endpoints. The USB receiver has a single
16-byte FIFO. When the USB controller is not enabled in the USMOD, it consumes minimal
power.
Note: After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are
transmitted, the TX buffer descriptor is closed. Additionally, the receive buffer is
closed after a frame is received. Any data received after 1,520 bytes or a single
frame causes a busy (out-of-buffers) condition since only one RX buffer
descriptor is prepared.