Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-181
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
16.9.8 Handling Interrupts In the SCC2
Interrupt handling for the SCC2 channel is configured on a global basis in the CPM interrupt
pending register, CPM interrupt mask register, and CPM in-service register. In each of these
registers, a bit is used to mask, enable, or report the presence of an interrupt from SCC2.
The interrupt priority between the serial communication controller is programmable in the
CPM interrupt configuration register. There is an event register within each protocol of the
serial communication controller that allows interrupt handling.
A number of events can cause the serial communication controller to interrupt the processor
and these events differ slightly depending on the protocol you have selected. These events
are handled independently between each channel by the SCC2 event and mask registers.
Events that can cause interrupts because of the CTS and CD modem lines are described in
16.9.8.1 SCC2 EVENT REGISTER. The 16-bit memory-mapped SCC2 event (SCCE)
register is used to report events recognized by the serial communication controller. When
an event is recognized, the serial communication controller sets the corresponding bit in the
SCCE, regardless of the corresponding mask bit. A bit is cleared by writing a 1 (writing a
zero has no effect) and more than one bit can be cleared at a time. This register is cleared
at reset and can be read at any time. Since each protocol has specific requirements, the
protocol-specific mode register (PSMR) bits are different for each implementation. A
detailed description of each of the PSMR bits is contained within each specific protocol.
16.9.8.2 SCC2 MASK REGISTER. The 16-bit, read/write SCC2 mask (SCCM) register
allows you to enable or disable interrupt generation using the communication processor
module for specific events in each SCC2 channel. An interrupt is only generated if the SCC2
interrupts in this channel are enabled in the CPM interrupt mask register (CIMR).
If a bit in the SCCM register is zero, the communication processor module does not proceed
with its usual interrupt handling whenever that event occurs. Anytime a bit in the SCCM
register is set, a 1 in the corresponding bit in the SCCE register sets the SCC2 bit in the CPM
Controller. The bit format of the SCCM register is identical to that of the SCCE. Since each
protocol has specific requirements, the SCCM bits are different for each implementation. A
detailed description of each of the SCCM bits is contained within each specific protocol.
16.9.8.3 SCC2 STATUS REGISTER. The 8-bit, read/write SCC2 status (SCCS) register
allows you to monitor real-time status conditions on the RXD2 signal. It does not show the
real-time status of the CTS and CD pins. Their real-time status is available in the port C
parallel I/O. Since each protocol has specific requirements, the SCCS bits are different for
each implementation. A detailed description of each of the SCCS bits is contained within
each specific protocol.