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| 型號(hào)： | MPC107APX66L0 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PPGA503 |
| 封裝： | PLASTIC, BGA-503 |
| 文件頁(yè)數(shù)： | 23/46頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107APX66L0 |
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MPC107 Hardware Specifications (Rev 0.2)
3
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Overview
1.1 Overview
The MPC107 integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers,
a message unit with an Intelligent Input/Output (I2O) message controller, and an Inter-Integrated Circuit
(I2C) controller. The integration reduces the overall packaging requirements and the number of discrete
devices required for an embedded system.
Figure 1 shows the major functional units within the MPC107. Note that this is a conceptual block diagram
intended to show the basic features rather than an attempt to show how these features are physically
implemented.
Figure 1. MPC107 Block Diagram
60x Bus Interface (64- or 32-Bit Data Bus)
Address
Translator
DLL
Fanout
Buffers
PCI
Arbiter
Message
Unit
(with I2O)
I2C
Controller
DMA
Controller
Interrupt
Controller
EPIC
/Timers
PCI Bus
Interface Unit
Memory
Controller
Data Path
ECC Controller
Central
Control
Unit
32-Bit
OSC_IN
Five
Request/Grant
Pairs
I2C
5 IRQs/
Peripheral Logic Block
PLL
PCI Bus
Data (64-Bit)
Address
Data Bus
(64- or 32-bit)
Memory/ROM/
Port X Control/
PCI Interface
Clocks
16 Serial
Interrupts
Configuration
Registers
(32-Bit)
with 8-bit Parity
or ECC
MPC107
PCI_SYNC_IN
Address
SDRAM Clocks
CPU Clocks
SDRAM_SYNC_IN
Additional features:
Programmable I/O
with Watchpoint
JTAG/COP Interface
Power Management
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