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參數(shù)資料
| 型號： | MPC107APX66L0 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PPGA503 |
| 封裝： | PLASTIC, BGA-503 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 585K |
| 代理商： | MPC107APX66L0 |
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24
MPC107 Hardware Specifications (Rev 0.2)
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Notes:
1
Units for these specications are in SDRAM_CLK/CPU_CLK units.
2
The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in
the frequency divider register I2CFDR. Therefore, the noted timings in the above table are all relative to
qualied signals. The qualied SCL and SDA are delayed signals from what is seen in real time on the
I2C bus. The qualied SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFS
times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The resulting delay value is added to the value in the table
(where this note is referenced). See Figure 13.
3
Since SCL and SDA are open-drain type outputs, which the MPC107 can only drive low, the time
required for SCL or SDA to reach a high level depends on external signal capacitance and pull-up resistor
values.
4
Specied at a nominal 50pF load
5DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to the I
2C Interface chapters Serial
Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit
x. N is equal to a variable number that would make the result of the divide (Data Hold Time value) equal
to a number less than 16. M is equal to a variable number that would make the result of the divide (Data
Hold Time value) equal to a number less than 9.
Table 14. I2C Output AC Timing Specifications
At recommended operating conditions (See Figure 2) with GVdd = 3.3 V ± 5% and LVdd = 3.3 V ± 5%
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) x (DFDR/16) / 2N +
(FDR[5] == 1) x (DFDR/16) / 2M
CLKs
1,2,5
2
Clock low period
DFDR / 2
CLKs
1,2,5
3
SCL/SDA rise time
(from 0.5 V to 2.4 V)
mS
3
4
Data hold time
8.0 + (16 x 2FDR[4:2]) x (5 -
4({FDR[5],FDR[1]} == b10) -
3({FDR[5],FDR[1]} == b11) -
2({FDR[5],FDR[1]} == b00) -
1({FDR[5],FDR[1]} == b01))
CLKs
1,2,5
5
SCL/SDA fall time
(from 2.4 V to 0.5 V)
< 5
ns
4
6
Clock high time
DFDR / 2
CLKs
1,2,5
7
Data setup time
(MPC107 as a master only.)
(DFDR / 2) - (Output data hold time)
CLKs
1,5
8
Start condition setup time
(for repeated start condition only)
DFDR + (Output start condition hold
time)
CLKs
1,2,5
9
Stop condition setup time
4.0
CLKs
1,2
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